As shown in FIG. 1, standard CMOS devices typically include a drain region 100 and a source region 102 formed on either side of a polysilicon gate 104, which is separated from the substrate by an oxide layer 106. Contact to the drain 100 and source 102 is achieved through a silicide layer 108. To ensure that the gate 104 and drain and source silicide 108 are not shorted a spacer is formed on either side of the gate 104 prior to forming the drain region 100 and source region 102 and prior to silicidation. Each spacer comprises an oxide liner 110 and a nitride spacer 112 as shown in FIG. 1. Since the bottom portions of the spacers adjacent the polysilicon gate 104 largely dictate the gate-drain capacitance and gate-source capacitance (also referred to as the fringing capacitance), it will be appreciated that the fringing capacitance can be reduced by increasing the width of the spacer. However, since this also increases source and drain resistance, the oxide liner has typically been limited to a thickness of about 200 Å and the nitride spacer thickness or length to about 1000 Å.